Cadence says its AI-driven chip design tools provide a process node’s worth of performance gain, but without moving forward to a new node

Anirudh Devgan, the CEO of Cadence, recently remarked that the company’s AI-assisted chip design tools enable chip performance and density benefits similar to the transition to a next-generation process node, but without moving to a new node. Devgan cited strong performance, power, and area (PPA) improvements, the most important metrics for chipmakers (along with cost), and also cited drastic improvements in productivity and examples with the company’s own custom processors. 

Discussing the EDA company’s latest suite of AI-assisted software tools, Devgan said, “So, overall, we are pleased with the benefit we are getting, especially with the improvement in PPA. And productivity improvements can be anywhere between 5x to 10x, but the PPA benefits are truly remarkable and almost equivalent to one kind of node. One process node migration typically gets [s] 15% to 20% PPA improvement, and we can get that with AI.”

“As you may know, we have five major AI platforms [in the Cadence.AI portfolio], analog, digital, verification, PCB and package and system analysis, it is a pretty rich portfolio,” said Anirudh Devgan, chief executive of Cadence, during the company’s earnings conference call with analysts and investors (via SeekingAlpha). “The customers are routinely seeing anywhere from 5% to 20% improvement in PPA, which is significant.”

Modern process technologies give fairly limited node-to-node performance and transistor density scaling. Compared to TSMC’s N5 (a 5nm-class process technology), the company’s N3 (a 3nm-class node) offers a 10% to 15% performance improvement, and TSMC promises a similar enhancement for N2 compared to N3. Therefore, getting up to a 20% performance boost by just using a set of AI-optimized tools is a very significant achievement akin to a step forward to a new node.

Cadence is primarily known for its electronic design automation (EDA), simulation, and prototyping software for chip development. However, not everyone knows that the company also designs its own Palladium processors, some of the most complex chips built by TSMC, to accelerate simulation workloads. Enhancing performance and increasing the transistor density of these Palladium processors is crucially important for Cadence, both from a competitiveness and cost point of view. Therefore, the company uses its own tools to refine design of these processors and get these benefits as well.

“We are also applying our own solutions internally,” Devgan added. “So, these are like true comparisons of AI versus non-AI solutions. So even in the latest Palladium Z3 chip, we saw like a 15% improvement in power using Cadence Cerebrus. In the latest AI IP we designed, we saw anywhere from 13% to 20% improvement in our IP group using our own Cadence.AI solutions, which is very consistent with what we see with top customers.” 

Beyond PPA enhancements, the company claims Cadence’s AI tools drive substantial productivity increases, often ranging between 5 to 10 times the usual output. If borne out, this level of efficiency should make the Cadence.AI portfolio a very compelling offering for an industry that has to build more sophisticated designs that offer higher performance than their predecessors while managing costs.